Anunciado 22 de febrero 
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Descripción del empleo
  • Multinational company that provides with comprehensive end-to-end solutions|Full remote position

Multinational company that provides with comprehensive end-to-end solutions that generate continuing value with HQ based on Madrid but with different co-working all over Spain.




  • (Floorplanner Lead): Industry Experience 6-10years
    • Tapeout experience in full chip floorplan/full chip partitioning flow. Experience in die-size estimation - spread sheet IP based and synthesis based

    • Experience in IO/Bump planning & placement, custom analog/PG planning and route implementation

    • Experience in ICC2/Innovus/DC tools, Fusion compiler being added advantage. Experience in RDL routing

    • Experience in interfacing with cross functional teams and block PnR teams

    • Good understanding of basic shell scripting, tool based TCL scripting to automate all custom activities

    • Experience in version control systems.

    • Experience in managing/mentoring small teams.


  • (Clocking Lead): Industry Experience 6-10years
    • Multiple tapeout experience in full chip PnR for lower node technologies.

    • Thorough understanding of different clocking architecture and their impact on chip performance

    • Experience in ICC2/Innovus/DC tools, Fusion compiler being added advantage

    • Experience in ETM/QTM based full chip PnR including synthesis

    • Prior experience in defining clock constraints and derates in conjunction with technology and front end design team. Full chip CTS methodology planning/implementation.

    • Experience in interfacing with cross functional teams and block PnR teams

    • Good understanding of basic shell scripting, tool based TCL scripting to automate all custom activities

    • Experience leading team of significant strength. Experience in managing/mentoring small teams.

    • Experience in version control systems.


  • (Static Timing analysis flows) Industry Experience : +8years
    • Experience in Multi-mode/Multi-corner runs.

    • Constraints development and management of multi partition design and top level. Chip Level IO timing closure. Experience in FUNC/DFT timing closure

    • Experience in analysis of timing paths to identify key issues. Timing Convergence ( Both Inter/Intra block Level). Understanding of noise, cross-talk, OCV effects, margins, and constraints.

    • Experience in timing and power ECO techniques and implementation

    • Automation Skills using scripting languages like TCL/PERL/Python/SHELL. Tools - Primetime/Tempus




  • (Physical Verification Lead) Industry Experience : 6-10years
    • Develop fullchip flows and own physical design verification, analysis & signoff in advanced technology nodes. Owned and delivered the fullchip tapeout gds requirements for one or more designs.

    • Must have experience in TSMC/Intel 16/10nm technology node or below.

    • Experience in analyzing and solving DPT(double/multiple patterning) loop issues.

    • Experience in analyzing fullchip LVS, PG shorts & related issues. Debug and fixing of fullchip DRC, MRC, Antenna, latchup, ERC, PERC issues.

    • Use EDA tool-based programming and scripting techniques to automate and improve throughput and quality.

    • Must have hands-on experience in Mentor Calibre/Synopsys ICV/Cadence PVS. Experience in chip integration using gds merge tools or Virtuoso.

    • Experience in Innovus/ICC2 is good to have.

    • Prior experience in leading a PDV team of 2-5 engineers for blocks & fullchip tapeout closure.


  • (Reliability [EM/IR] Verification Lead) Industry Experience : 6-10years
    • Develop fullchip flows and own IR drop, EM analysis & signoff in advanced technology nodes.

    • Resolve fullchip design and flow issues related to PDN (power distribution network), identify potential solutions and interface with PD team to get the change implemented.

    • Experience in fullchip running mesh resistance, static, dynamic IR/EM checks, analyzing the results and providing solutions.

    • Able to review design requirements and decide on vectorless simulation duration, VCD cycle selection.

    • Ability to run Redhawk with DFT VCD patterns and provide solutions for issues.

    • Able to generate fullchip STA timing file based on PrimeTime/Tempus timing session.

    • Must have hands-on experience in Ansys Redhawk or Redhawk-SC or Cadence Voltus.

    • Experience in Innovus/ICC2 is good to have.

    • Use EDA tool-based programming and scripting techniques to automate and improve throughput and quality.

    • Prior experience in leading a PDN team of 2-5 engineers for blocks & fullchip PDN closure.

    • Owned and delivered the fullchip tapeout PDN requirements for one or more designs.

    • Experience in TSMC/Intel 16/10nm technology node or below is good to have.

    • Experience in Redhawk package based (CPA) analysis is a good to have.



Working on a multinational company with a full remote position to work for big companies based on Spain but most of them in Barcelona.




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